DigSimul49 v4.beta – Digital Simulator for the HP49

1. Overview

This is a library intended to simulate a simple digital circuit. Where “simple” means a digital circuit based on simple gates (AND, OR, etc.). It understands eleven primitives and nested macros.

The idea of this library comes directly from the one done by Tony Duell in October 1990 (DIGSIMUL available at www.hpcalc.org ) in user-rpl. This one is done in SysRPL and ML (scroll.max routine not mine).

This is not a port to SysRPL of the original, it is mainly done from the scratch but following the Tony’s original ideas.

2. Disclaimer

The library is distributed 'as is' and is subject to change without notice. No warranty of any kind is made with regard to the software or documentation. The author shall not be liable for any incidental error or consequential damages in connection with the software and/or the documentation.

DigSimul49 can be freely distributed provided this manual is distributed with it without any modification. DigSimul49 can't be used for any commercial purpose without written permission from the author. This implies the user shouldn't be charged for the use of this software.

Remember as well that I only work on RPN mode so no test is made for ALG mode.

English is not my native language so please excuse all my linguistic mistakes.

3. Backup

This software has been tested by me and seems to be safe but like always please backup your memory before trying it. It’s done 95% in SysRPL and 5% ML (scroll.max routine) with MASD so if there is any bug I haven’t detected you could loose you data L

Please take in account that this is a beta version, I finish my studies long time ago so I’m not working with this software and then I’m testing hardly.

4. History and Credits

The idea of this software is taken from one done for the HP48sx long time ago: DigSimul by Tony Duell which is available in www.hpcalc.org .

So in December'1995 I did my first SysRPL version of that software for my old sx, adding more primitives, and use it a lot in laboratory practices. Many years late comes the 49 and I start porting it to my new calc but adding a better user interface.

So my credit goes for:

- Tony Duell ( DigSimul in 1990 ).

4.1 Version History

v4 First Public Release on 49. Added a new GUIs. More checks done. Really it’s a beta.

v1,v2,v3 Private version on the 48.

4.2 To Do List

The most important thing to improve is the speed, specially the simulator. This version is very quick but I have in mind various improvements in ML and using the new features in the Rom of the 49 which will make this a lot more quicker. Unfortunately I’m not using it now so I’ve not very pressed on doing them. If you use this and you find it useful please let me know and surely I will recover my energies on it.

5. Installation

This program is a library. Its number is 1743 which I hope is not used. To install it you should transfer it to your HP in binary mode. Recall its contents and store it in any of your ports. Now you can purge the variable from where you download it. Then you should restart your HP.

At this point you could access to its menu in the Lib menu [LS][2] hint [NXT] if necessary. Or using 1743 MENU.

To uninstall it you should do:

1743 DEATTACH [ENTER]

:port:1743 PURGE [ENTER]

Other way of accessing and uninstalling this library is with the 49’s Filer which is pretty good in this. Look for it in the port were you stored it.

6. Circuit Description

The circuits in this library are a list of gates. Each gates is defined with a list (then sublist) which in general has the next format:

{ “Name” arg1 arg2 arg3….}

There “Name” is the name of any of the eleven primitives or a name of a variable (as string) that contains a subcircuit (a macro). The rest of the arguments are in general valid 49 identifiers (that represents nodes in the circuit) or integers and arrays (in the case of CLK, IN and INN primitives).

So a gate like { “AND” a1 a2 Both } defines an AND gate where ‘a1’ and ‘a2’ are the inputs and ‘Both’ is the output.

In the primitives the inputs are always given first and I suggest you to do so in the macros as Tony Duell did in the original DigSimul.

Let’s see the primitives. In all the cases the inputs comes from the previous step and the outputs conforms the next step. This is a digital circuit simulator simplified. It doesn’t take in account transitions in the states nor voltages. But with the use of the CLK you can take in account the delays a real circuit presents not accurately but approximately.

Two-Gate Primitives

In this area we got five primitives:

· AND:

It defines an AND gate. As we saw it’s format is:

{ “AND” inputID1 inputID2 outputID }

So {“AND” i1 i2 out} represents logically [out = i1 AND i2]. Remember that you should enter the list format not the last logical format.

· OR:

{“OR” i1 i2 out} represents [out = i1 OR i2 ]

· NAND:

{“NAND” i1 i2 out} represents [ out = i1 NAND i2 = NOT ( i1 AND i2 ) ]

· NOR:

{“NOR” i1 i2 out} represents [ out = i1 NOR i2 = NOT ( i1 OR i2 ) ]

· XOR:

{“XOR” i1 i2 out} represents [ out = i1 XOR i2]

One-Gate Primitives

Here we got two primitives:

· NOT:

This is the logical negation of the input. So:

{“NOT” A B} represents [ B = NOT A ]

· BUF:

This is only the buffering of the input. In other words it introduces a delay of one step because its output is the input which comes from the previous step.

{“BUF” A B}represents [ B = A ]

Tied Primitives

A node could also be defined with a permanent state high or low:

· HI:

{“HI” A} represents [ A = 1 ]

· LO:

{“LO” A} represents [ A = 0 ]

Clock Primitive

This is the key point of any digital circuit simulator like this one. The high and low states of the clock are defined in terms if steps. Each step represent one pixel column in the final graphic representation. The syntax of the primitive is as follows:

{“CLK” hi_steps lo_steps out}

So {“CLK” 5 3 clock} represents that clock will be 5 steps in high state then 3 steps in low then again 5 in high and so on.

Input Primitives

A real circuit has always some inputs from the outside. For represent that there are two primitives (which there aren’t in the Tony’s version, that where I started working). Of course in the 49 we don’t have real inputs so they are simulated with this primitives. Really we can have inputs with the serial port but I don’t know how to access it in that manner and it will make this library a lot more complex. There should be products for that kind of things (in the 48 there are I think).

· IN:

This primitive is intended to define a set of inputs for a node. This is the state the node has over the time (steps). Its syntax is:

{“IN” steps outNode [datas]}

Where steps indicate the number of steps each state given in [datas] remains. OutNode is the name of the node which follows this definition and [Datas] is a vector of real 0s and 1s. It’s cyclic so when the vector finish the node starts again.

· INN:

This one is for defining multiple nodes at the same time. I found it’s a lot more comfortable to define all the inputs together. It’s syntax is:

{“INN” steps node1 node2 … nodeN [[datas]]}

Where steps acts like in the IN primitive and [[datas]] is an array which should have N columns (if there is N node names).

Macro Primitives

The macros in a circuit simulator are like the sub-routines in programming. It’s very cumbersome to describe a circuit from the scratch so normally you build it in blocks. Here is where comes the macros.

So you can define a circuit. Test it. And then store it as a macro to be used by other circuits.

The syntax for a macro is as follows:

{ { list of all the nodes} {{the circuit}} }

Where the list of all the nodes should include in inputs, the outputs and all the internal ones. And the circuit is a valid circuit. This should be stored in a variable, ‘foo’ for example. Then you can refer it from other circuits using the next syntax:

{“foo” id1 id2 id3….}

Where all the ids represent the name in the new circuit for all the nodes in the macro, all the nodes in the first list of the macro definition. The macro is replaced at compiling time (see below) so you give a name for all the nodes and they are accessible for the simulator. The macro becomes part of the circuit.

Lets see an example, a 2bit MUX.

Where we see the inputs Sel, inA and inB and the output outY. For our purpose we must describe the internal nodes as well (in red):

Given this circuit its definition will be:

{

{ “NOT” SEL NS}

{ “AND” NS inA tA}

{ “AND” SEL inB tB}

{ “OR” tA tB outY }

}

And for be a macro:

{

{ SEL inA inB outY NS tA tB }

{

{ “NOT” SEL NS}

{ “AND” NS inA tA}

{ “AND” SEL inB tB}

{ “OR” tA tB outY }

}

As you see I put (like Tony Duell) the inputs and outputs first in the macro definition.

So if this is stores in a variable MUX (like in the models.src included) you can use the next in your circuits: {“MUX” X Y Z GO auxZ auxY auxZ}.

With the next mapping:

X	SEL
Y	inA
Z	inB
GO	outY
auxX	NS
auxY	tA
auxZ	tB

7. Description of the simulator

This simulator is composed of two parts. The compiler and the Simulator. The compiler takes a circuit described with the above format and generates an internal description of it, substituting the macros, storing it in a CircPAR variable of type library format. While you don’t change the circuit or any of the macros used by it you can simulate it without recompiling.

The simulator takes the initial step number and the final step number and generates a HI-LO graph of the circuit for the selected nodes.

You can use it from command line with the commands provided or use the graphic user interface commands.

8. Command Description

NewSimul:

This command takes a circuit from the stack, compiles it and then gives you a graphical interface to simulate it. Let’s take as example the circuit stored in the sample ‘Models.src’ directory: ‘Example.src’. Recall it and press [NewSimul], it compiles the circuit and gives you a browser to select which variables to show in the simulation and order them (this idea –ordering- is taken from List Reorder v1.0 from Beto –see www.hpcalc.org). You can see it in the next image:

It has the next menu options:

· Up: Moves the current node up.

· Down: Moves the current node down.

· CHK: Check/Uncheck the current node to be included in the simulation.

· All: Checks all nodes.

· All: Unchecks all nodes.

· Cancel: Exits the simulation.

· Simulate: Start simulation.

If you uncheck everything, then check the first five as in the image and then press Simulate you pass the an InputForm where you must indicate the step range of the simulation:

Pressing [Cancel] returns to the browser and pressing [OK] starts the simulation:

The result image is shown with the scroll.max grob viewer (thanks to Lillian Pigallio). The reason of doing this is because the internal grob viewer starts from the bottom instead from the top. The keys in this viewer are F1-F6 to select speed, arrows to move the grob and backspace to exists which will returns you to the nodes selection browser.

DoSimul:

This command launch a simulation session with the previous compiled circuit (CircPAR should be present). It’s the same than [NewSimul] but without the compilation.

SimulCir:

This command takes to reals from the stack and simulates the circuit already compiled with the already selected nodes (done with NewSimul, DoSimul or the specific commands described below) using the two reals as step range.

CompileCir:

This command takes a circuit definition from the stack, compiles it and sets all nodes as checked nodes.

outIDà:

This command gives you the current checked nodes of the circuit in CircPAR.

allIDà:

This command gives you all the nodes of the circuit in CircPAR.

àoutID:

This command sets the checked nodes for the circuit in CircPAR.

9. Example directory.

The library comes with an example directory Modules.src which contains one example circuit Example.src and four macros:

· MUX: A 2-bits Multiplexor

· MUX4: a 4-bits Multiplexor

· HADD: a half adder.

· FADD: a full adder.

They come from the original Tony Duell examples, properly modified for my macro format.

10. Final Remarks

Library is ID 1743. Its size is 4275.5 bytes and its checksum is #517Dh.

The library have done in SysRPL, but I use an ML grob viewer by L.Pigallio.

It’s completely done in the HP49 with Masd, Emacs, InFormBuilder and the help of Nosy.

I really hope this will useful for you.

11. Acknowledgements

I would like to thank to:

· Mika Heiskanen. His Entries.src discovered me the insides of my 48sx.

· Alex Ramos. His RPL++ compiler let me start to work in SysRPL without the complexities I found with HP ones.

· Detlef Mueller and Raymond Hellstern for RPL48

· C.Bourgeois (BOUHP). The ‘Kernel’ stack replacement discovered me a new work and force me to do a really good job on my sx.

· Jean Yves Avenard. StringWriter! How do you do it?

· Bernard Parisse. The ALGB (the Erables’s father) makes me realize that the 48 could do magic.

· ACO for the Hp49.

· Carsten Dominik and Peter Geelhoed for Emacs

· Jurjen N.E. Bos for Nosy.

· Steen S. Schmidt for InFormBuilder.

· Beto for List Reorder v1.0 which gives me ideas for my browser.

· Lillian Pigallio for Scroll.max routine.

· Tony Duell for his original DigSimul.

11. Contact

As I explain in the disclaimers part this is freeware but I spent a lot of time on it so I’ll really thank any email telling me what do you think about it of if you find any bug or have any idea to extend it.

Luis Morales Boisset

lboisset@arrakis.es